Title :
High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application
Author :
Chen, Chun-Yu ; Lin, Jyi-Tsong ; Chiang, Meng-Hsueh ; Kim, Keunwoo
Author_Institution :
Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
Comparison of junctionless and conventional nanowire FETs is presented. Our numerical simulation results suggest that though the junctionless device suffers low drive current due to its accumulation nature, it has an advantage in scalability. Relaxed wire diameter requirement is predicted for the junctionless case. More interestingly, it shows a great potential in ultra-low power subthreshold logic application due to superior speed, as compared with the conventional structure.
Keywords :
field effect transistors; low-power electronics; nanowires; silicon-on-insulator; threshold logic; SOI substrate; high-performance ultra-low power junctionless nanowire FET; junctionless device; low drive current; subthreshold logic application; ultra-low power subthreshold logic; wire diameter; Leakage current; Logic gates; Nanoscale devices; Performance evaluation; Transistors; Wire;
Conference_Titel :
SOI Conference (SOI), 2010 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-9130-8
Electronic_ISBN :
1078-621x
DOI :
10.1109/SOI.2010.5641061
