DocumentCode
3168349
Title
Evaluation of architecture-level power estimation for CMOS RISC processors
Author
Sato, T. ; Ootaguro, Y. ; Nagamatsu, M. ; Tago, H.
Author_Institution
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
fYear
1995
fDate
9-11 Oct. 1995
Firstpage
44
Lastpage
45
Abstract
An evaluation of the architecture-level power estimation simulator, ESP (Early design Stage Power and performance simulator), is presented. With ESP, it is possible to accomplish more efficient design by using the architecture-level and gate-level simulator correctly. The estimation and the actual measured results are very similar. In addition, the accuracy of ESP has been improved by 18.3%.
Keywords
CMOS digital integrated circuits; computer architecture; digital simulation; instruction sets; integrated circuit design; microprocessor chips; reduced instruction set computing; CMOS RISC processors; ESP; architecture-level power estimation; architecture-level simulator; gate-level simulator; power estimation simulator; stage power; CMOS process; Circuit simulation; Clocks; Design engineering; Electrostatic precipitators; Power dissipation; Power engineering and energy; Reduced instruction set computing; Research and development; Semiconductor devices;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location
San Jose, CA, USA
Print_ISBN
0-7803-3036-6
Type
conf
DOI
10.1109/LPE.1995.482457
Filename
482457
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