• DocumentCode
    3168374
  • Title

    Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

  • Author

    Liu, Y.X. ; Sekigawa, T. ; Hayashida, T. ; Matsukawa, T. ; Endo, K. ; O´uchi, S. ; Sakamoto, K. ; Ishii, K. ; Tsukada, T. ; Ishikawa, Y. ; Yamauchi, H. ; Ogura, A. ; Koike, H. ; Suzuki, E. ; Masahara, M.

  • Author_Institution
    Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba
  • fYear
    2008
  • fDate
    6-9 Oct. 2008
  • Firstpage
    161
  • Lastpage
    162
  • Abstract
    The logic gate threshold voltage controllable single metal gate FinFET CMOS inverter constructed by the 3T-PMOS and 4T-NMOS have successfully been fabricated. The accurate current matching and the logic gate threshold voltage tuning by Vg2 in the 4T-NMOS have been demonstrated. A higher WF metal would be more suitable for the proposed FinFET CMOS.
  • Keywords
    CMOS logic circuits; MOSFET; etching; invertors; voltage control; 3T-PMOS; 4T-NMOS; logic gate threshold voltage; single metal gate FinFET CMOS inverters; wet etching; CMOS logic circuits; CMOS technology; Fabrication; FinFETs; Logic gates; MOS devices; Pulse inverters; Threshold voltage; Tin; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2008. SOI. IEEE International
  • Conference_Location
    New Paltz, NY
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-1954-8
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2008.4656344
  • Filename
    4656344
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3168374