Title :
An ultra-low-power CMOS on-chip interconnect architecture
Author :
Bellaouar, A. ; Abu-Khater, I.S. ; Elmasry, M.I.
Author_Institution :
Waterloo Univ., Ont., Canada
Abstract :
An ultra-low-power CMOS static on-chip interconnect architecture is proposed. It is based on using low-swing on the capacitive bus. The power due to the charging and discharging of the bus is reduced by a factor as high as 10 at 3.3 V without any delay degradation. The circuits are implemented in 0.8 /spl mu/m CMOS technology. The performance can be improved using multi-threshold voltage techniques without any increase in DC power.
Keywords :
CMOS digital integrated circuits; ULSI; VLSI; delays; integrated circuit interconnections; 0.8 micron; 3.3 V; DC power; ULSI; VLSI; bus charging; bus discharging; delay degradation; low-swing capacitive bus; multi-threshold voltage techniques; on-chip interconnect architecture; ultra-low-power CMOS; CMOS technology; Degradation; Delay; Driver circuits; Integrated circuit interconnections; Leakage current; MOS devices; Power dissipation; Threshold voltage; Very large scale integration;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482461
