An energy recovery static RAM memory core

In the design of low power circuits, recovered energy or adiabatic logic shows great promise. However work done till date has largely concentrated on implementing logic circuits/families using the principle of energy recovery. Today´s VLSI systems integrate random logic, megamodules and memories. Hence, the success of recovered energy logic will depend on the efficient implementation of not just random logic, but also the other components of a VLSI system. In this paper we present a Static Random Access Memory (SRAM) Core which operates on the principles of energy recovery, and can be implemented without compromising greatly on area or circuit complexity. The design addresses the issue of building very low powered memory circuits in VLSI systems. Our results indicates energy savings of 84% for read operations and 85% savings for write operations.