A universal Pezaris array multiplier generator for SRAM-based FPGAs

A new approach to implement fast array multipliers of any word length in SRAM-based FPGAs is presented. The proposed method is based on a generic FPGA model and, therefore, suitable for most commercial FPGA devices. Taking the logical structure of the multiplier into account, technology mapping including adaptive structure generation as well as signal flow driven placement and automatic partitioning are efficiently performed yielding implementations of higher performance and better resource utilization than previously published