Synthesis Method for Hierarchical Interface-based Supervisory Control

Hierarchical Interface-based Supervisory Control (HISC) decomposes a discrete-event system (DES) into a high-level subsystem which communicates with n ges 1 low- level subsystems, through separate interfaces which restrict the interaction of the subsystems. It provides a set of local conditions that can be used to verify global conditions such as nonblocking and controllability. As each clause of the definition can be verified using a single subsystem, the complete system model never needs to be stored in memory, offering potentially significant savings in computational resources. Currently, a designer must create the supervisors himself and then verify that they satisfy the HISC conditions. In this paper, we develop a synthesis method that can take advantage of the HISC structure. We replace the supervisor for each level by a corresponding specification DES. We then do a per level synthesis to construct for each level a maximally permissive supervisor that satisfies the corresponding HISC conditions. We define a set of language based fixpoint operators and show that they compute the required level-wise supremal languages. We then discuss the complexity of the algorithms that we have constructed that implement the fixpoint operators and show that they potentially offer significant improvement over the monolithic approach. A large manufacturing system example (estimated worst case statespace on the order of 10²²) extended from the AIP example is discussed. A software tool for synthesis and verification of HISC systems using our approach was also developed.