Title :
Transistor-level sizing and timing verification of domino circuits in the Power PCTM microprocessor
Author :
Dharchoudhury, A. ; Blaauw, D. ; Norton, J. ; Pullela, S. ; Dunning, J.
Author_Institution :
High Performance Design Technol., Motorola Inc., Austin, TX, USA
Abstract :
This paper describes a tool called Focus that is currently being used for the timing verification and siting of domino CMOS circuits in a Power PCTM microprocessor. Domino CMOS circuits introduce more complex timing and sizing requirements compared to conventional static circuits. This paper shows how these requirements are addressed in Focus. Some case studies involving the application of Focus on production circuits are also described
Keywords :
CMOS logic circuits; SPICE; microprocessor chips; timing; CMOS circuits; Focus; Power PCTM microprocessor; case studies; domino circuits; static circuits; timing verification; transistor-level sizing; CMOS technology; Circuit simulation; DH-HEMTs; Delay; Microprocessors; Phase change materials; Production; Robustness; Semiconductor device modeling; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8206-X
DOI :
10.1109/ICCD.1997.628861
