DocumentCode
316865
Title
Nonenumerative path delay fault coverage estimation with optimal algorithms
Author
Kagaris, Dimitrios ; Tragoudas, Spyros ; Karayiannis, Dimitrios
Author_Institution
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
1997
fDate
12-15 Oct 1997
Firstpage
366
Lastpage
371
Abstract
A recent method proposed that a lower bound on the number of path delay faults excited by a given test set can be computed using a set independent lines that form a cut. For each line in the cut a subcircuit consisting of all paths that contain the line is defined, and a lower bound to the number of excited path delay faults can be obtained by working on the respective subcircuits. A polynomial time algorithm is presented here for computing the maximum cardinality set of independent circuit lines. Experimental results show that the more the subcircuits the better the lower bound on the number of excited path delay faults is. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts Ci. We propose a technique where only one Ci must be a cut. This scheme is based on novel algorithms, and results in more subcircuits than the previous one
Keywords
combinational circuits; fault diagnosis; logic testing; combinational circuit; fault coverage estimation; lower bound; maximum cardinality set; optimal algorithms; path delay fault coverage; path delay faults; polynomial time algorithm; test patterns; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Delay estimation; Electrical fault detection; Fault detection; Microwave integrated circuits; Polynomials; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-8206-X
Type
conf
DOI
10.1109/ICCD.1997.628896
Filename
628896
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