DocumentCode
3168800
Title
Impact of CMOS scaling on single-event hard errors in space systems
Author
Johnston, A.H. ; Swift, G.M. ; Shaw, D.C.
Author_Institution
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fYear
1995
fDate
9-11 Oct. 1995
Firstpage
88
Lastpage
89
Abstract
Applications of highly scaled devices in space are shown to be limited by hard errors from cosmic rays. Hard errors were first observed in 0.8 /spl mu/m DRAMs. For feature sizes below 0.5 /spl mu/m, scaling theory predicts that low power devices will have much lower hard error rates than devices optimized for high speed.
Keywords
CMOS memory circuits; DRAM chips; cosmic ray interactions; integrated circuit testing; space vehicle electronics; 0.5 mum; 0.8 /spl mu/m DRAMs; 0.8 mum; CMOS scaling; cosmic rays; feature size; hard error rates; low power devices; scaling theory; single-event hard errors; space systems; CMOS technology; Cosmic rays; Error analysis; Laboratories; MOSFETs; Power supplies; Propulsion; Space technology; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location
San Jose, CA, USA
Print_ISBN
0-7803-3036-6
Type
conf
DOI
10.1109/LPE.1995.482476
Filename
482476
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