Title :
Multi-column implementations for cache associativity
Author :
Zhang, Chenxi ; Zhang, Xiaodong ; Yan, Yong
Author_Institution :
Changsha Inst. of Technol., Hunan, China
Abstract :
We propose two schemes for implementing higher associativity: the sequential multi-column cache, which is an extension of the column associative cache, and the parallel multi-column cache. In order to achieve the same access cycle time as that of a direct-mapped cache, data memory in the cache is organized into one bank in both schemes. We use the multiple MRU block technique to increase the first hit ratio, thus reducing the average access time. While the parallel multi-column cache performs the tag checking in parallel, the sequential multi-column cache sequentially searches through places in a set, and uses index information to filter out unnecessary probes. In the case of an associativity of 4, they both achieve the low miss rate of a 4-way set-associative cache. Our simulation results using ATUM traces show that both schemes can effectively reduce the average access time
Keywords :
DRAM chips; cache storage; memory architecture; performance evaluation; reduced instruction set computing; 4-way set-associative cache; ATUM traces; DRAM access time; RISC; VLSI technology; access cycle time; average access time; cache associativity; column associative cache; data memory; first hit ratio; multi-column implementations; multiple MRU block; parallel multi-column cache; sequential multi-column cache; simulation results; tag checking; Clocks; Costs; Educational institutions; Filters; Interference; Logic; Random access memory; Reduced instruction set computing; Very large scale integration; Whales;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8206-X
DOI :
10.1109/ICCD.1997.628915
