• DocumentCode
    3169105
  • Title

    A novel DS-CDMA RAKE receiver: architecture and performance

  • Author

    Huang, K.B. ; Chew, Y.H. ; Chin, P.S. ; Heng, K.T.

  • Author_Institution
    Inst. for Infocomm Res., Singapore, Singapore
  • Volume
    5
  • fYear
    2004
  • fDate
    20-24 June 2004
  • Firstpage
    2904
  • Abstract
    A DS-CDMA RAKE receiver architecture is proposed. Unlike the conventional receiver, the proposed ΣΔ-CDMA receiver does not require a ΣΔ demodulator and a root-raised-cosine (RRC) filter, and hence its despreader can be implemented mainly using simple XNOR gates and 2-bit adders. The conditional BER for DS-CDMA forward link is derived and the averaged BER is obtained by Monte Carlo simulation. It is shown that the BER performance of the proposed receiver can match that of the conventional DS-CDMA receiver, which is implemented using a ΣΔ analog-to-digital converter (ADC), with the proper choice of over-sampling ratio. And the proposed receiver achieves a much smaller gate-count than the conventional receiver when implemented on FPGA.
  • Keywords
    Monte Carlo methods; code division multiple access; error statistics; field programmable gate arrays; radio receivers; sigma-delta modulation; signal sampling; spread spectrum communication; ΣΔ-CDMA receiver; BER; DS-CDMA Rake receiver; FPGA; Monte Carlo simulation; XNOR gates; analog-to-digital converter; bit error rates; field programmable gate arrays; forward link; Bit error rate; Demodulation; Fading; Filters; Hardware; Microprocessors; Multiaccess communication; Multipath channels; RAKE receivers; Signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, 2004 IEEE International Conference on
  • Print_ISBN
    0-7803-8533-0
  • Type

    conf

  • DOI
    10.1109/ICC.2004.1313060
  • Filename
    1313060