A 1.4 M-transistor CMOS gate array with 4 ns RAM

Author

Takahashi, T. ; Kawashima, M. ; Fujita, M. ; Kobayashi, I. ; Arai, K. ; Okabe, T.

Author_Institution

Hitachi, Tokyo, Japan

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

178

Lastpage

179

Abstract

A submicron CMOS gate array implemented with 0.8- mu m triple-metal-layer process technology is presented. The chip includes 1.4 M transistors which can be used as 130k logic gates, and a 38-kb SRAM (static random-access memory) and is housed in a 400-pin pin-grid array-package. Typical gate delay time is 0.35 ns, and SRAM access time is 4.0 ns. The process parameters are shown, and the basic features of the chip are listed. A memory controller for a general-purpose, 64-b CPU has been fabricated on this gate array in order to prove feasibility. Systematic placement and the equal load capacitance of the clock drivers make maximum clock skew time +or-1.0 ns within the chip.<>

Keywords

CMOS integrated circuits; VLSI; logic arrays; random-access storage; 0.35 ns; 38 kbit; 4 ns; CMOS gate array; RAM; SRAM; VLSI chip; access time; gate delay time; memory controller; pin-grid array-package; static random-access memory; submicron; triple-metal-layer process; CMOS logic circuits; CMOS process; CMOS technology; Capacitance; Clocks; Delay effects; Logic arrays; Logic gates; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48249

Filename

48249