Architecture of the WE32200 chip set

Author

Nelson, Matthew S. ; Cruz-Rios, J. ; Ng, B. ; Wu, W.S.

Author_Institution

AT&T Inf. Syst., Holmdel, NJ, USA

fYear

1988

fDate

Feb. 29 1988-March 3 1988

Firstpage

43

Lastpage

47

Abstract

Four members of the WE32200 chip set are described. They are the WE32200 central processing unit (CPU), the WE32201 memory management unit (MMU), the WE32204 direct memory access controller (DMAC), and the WE32206 math acceleration unit (MAU). These chips constitute the VLSI core of a general-purpose computing environment supporting virtual memory and IEEE standard floating point arithmetic. The internal architecture of the microprocessor is presented, and the novel features of the four units are examined.<>

Keywords

computer architecture; microprocessor chips; IEEE standard floating point arithmetic; VLSI core; WE32200 chip set architecture; WE32201 memory management unit; WE32204 direct memory access controller; WE32206 math acceleration unit; central processing unit; general-purpose computing environment; virtual memory; Arithmetic; CMOS technology; Central Processing Unit; Kernel; Memory management; Microprocessors; Operating systems; Protocols; Registers; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-0828-5

Type

conf

DOI

10.1109/CMPCON.1988.4825

Filename

4825