DocumentCode
316940
Title
The impact of lot-to-lot and wafer-to-wafer variations on SPC
Author
Nurani, Raman K. ; Shanthikumar, George
Author_Institution
KLA Instruments Corp., San Jose, CA, USA
fYear
1997
fDate
35589
Firstpage
110
Lastpage
112
Abstract
In-line process control using SPC (statistical process control) charts is very well known for a long time. A vast amount of work has been done and extended in the area of optimal process control with sampling and control charts. However, the usage of standard process control charts for monitoring the defects during wafer fabrication could lead to serious errors. Specifically, this error arises due to the difference in the lot-to-lot and wafer-to-wafer variances of the in-line defect measurements. The purpose of this paper is to present the results of a new SPC model which explicitly accounts for the lot-to-lot and wafer-to wafer variations. We illustrate that the application of traditional policies could lead to suboptimal results by as much as 17%. Note that the traditional SPC charts are based on the assumption that the measurements are independent and identically distributed
Keywords
semiconductor process modelling; statistical process control; SPC model; defect measurement; lot-to-lot variation; optimal in-line process control; sampling; semiconductor manufacturing; statistical process control chart; wafer fabrication; wafer-to-wafer variation; Control charts; Error correction; Etching; Fabrication; Instruments; Monitoring; Optimal control; Process control; Sampling methods; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Statistical Metrology, 1997 2nd International Workshop on
Conference_Location
Kyoto
Print_ISBN
0-7803-3737-9
Type
conf
DOI
10.1109/IWSTM.1997.629426
Filename
629426
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