Title :
Statistical simulation methodology for multi-level interconnect contact analysis and step coverage evaluation
Author_Institution :
Silvaco Japan, Yokohama, Japan
Abstract :
Multi-level interconnect contact step coverage was simulated statistically varying wide range of etching/deposition model parameter and process condition
Keywords :
integrated circuit interconnections; semiconductor process modelling; deposition; etching; multi-level interconnect contact step coverage; process model; statistical simulation; Analytical models; Calibration; Data mining; Design methodology; Plasma applications; Plasma sheaths; Plasma simulation; Semiconductor device modeling; Sputter etching; Surfaces;
Conference_Titel :
Statistical Metrology, 1997 2nd International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-3737-9
DOI :
10.1109/IWSTM.1997.629427
