Model for worst case delay analysis of an AFDX network using timed automata

AFDX (Avionics Full Duplex Switched Ethernet) standardized as ARINC 664 is a major upgrade for avionics systems. But guarantees on upper bounds of end-to-end communication delays are required for certification purposes. The objective of this paper is to present an improved modeling approach using timed automata for calculation of exact worst case delays. This approach takes advantage of local scheduling of flows. Moreover, it can cope with larger network configurations than existing approaches based on timed automata, thanks to a port by port analysis which reduces the search space.