A 50 k-gate ECL array with substrate power supply

In microprocessor and system LSIs having several tens of thousands of gates, performance is determined by interconnection delay rather than by intrinsic gate delay because of limitations on total power consumption. This difficulty can be overcome if bipolar circuits can be made with density comparable to that of MOS circuits. To this end a bipolar technique using five interconnection layers is applied to an ECL (emitter-coupled-logic) gate array containing 53912 equivalent gates on a 7.8-mm*8.2-mm chip. The gate density is 843 gates/mm/sup 2/ for the chip and 1159 gates/mm for the internal cell region. The density results in short interconnections which reduces line delay, the major factor affecting VLSI performance. An emitter-base self-aligned structure with polysilicon electrodes and resistors (ESPER) combined with U-groove isolation with thick field oxide is employed in the device. Chip parameters and circuit schematics are presented.<>