Title :
A CMOS 2- and 4-FSK demodulator for direct-conversion radio paging receivers
Author :
Chen, Zhiheng ; Zhang, Zhaofeng ; Lau, Jack
Author_Institution :
Dept. of Radio Eng., Southeast Univ., Nanjing, China
fDate :
29 June-1 July 2002
Abstract :
The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in this paper. The demodulator is intended for use in direct-conversion high speed radio paging receivers. It is based on a zero-crossing counting and comparing scheme. To improve the bit error rate (BER) performance, a novel technique is utilized, which increases the decision accuracy by generating additional zero-crossings. Simple yet effective clock recovery circuits are included on-chip. The demodulator is fabricated in a 0.35 micron N-well CMOS process and occupies about 0.78 mm2 area. It consumes about 3 mW from a 3-V power supply. Good agreement between measurement and simulation is observed.
Keywords :
CMOS digital integrated circuits; circuit simulation; demodulators; error statistics; frequency shift keying; integrated circuit design; integrated circuit measurement; integrated circuit modelling; paging communication; radio receivers; synchronisation; 0.35 micron; 3 V; 3 mW; BER; CMOS 2-FSK demodulator; CMOS 4-FSK demodulator; IC design; IC measurement; N-well CMOS process; bit error rate performance; decision accuracy; direct-conversion radio paging receivers; frequency shift keying; on-chip clock recovery circuits; power supply; simulation; zero-crossing counting/comparing scheme; Bit error rate; CMOS technology; Circuits; Clocks; Demodulation; Frequency shift keying; Lifting equipment; Modulation; Phase detection; Receivers;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179018
