DocumentCode
3169988
Title
Introducing redundant transformations for built-in self-testable data path allocation
Author
Yang, Laurence Tianruo ; Muzio, Jon
Author_Institution
Dept. of Comput. Sci., Saint Francis Xavier Univ., Antigonish, NS, Canada
Volume
2
fYear
2002
fDate
29 June-1 July 2002
Firstpage
1346
Abstract
In our previous work, we described a high-level data path allocation algorithm to facilitate built-in self-test designs. In this paper, we make use of two types of redundant transformations, which add redundancy that improves test resources to be shared in the data path, to improve our previous data path allocation algorithm. The algorithm generates self-testable data path design while maximizing the sharing of modules and test registers. The sharing of modules and test registers enables only a small number of registers to be modified for BIST, thereby decreasing the hardware area which is one of the major overheads for the BIST technique. With a variety of benchmarks, we demonstrate the advantage of our approach compared with our previous and other conventional approaches.
Keywords
built-in self test; circuit optimisation; design for testability; integrated circuit design; integrated circuit testing; logic testing; redundancy; BIST technique; built-in self-test designs; built-in self-testable data path allocation; hardware area overhead; high-level data path allocation algorithm; module sharing; redundancy; redundant transformations; self-testable data path design; test register sharing; test resources; Algorithm design and analysis; Built-in self-test; Circuit testing; Digital circuits; Hardware; Iterative algorithms; Logic testing; Registers; Resource management; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN
0-7803-7547-5
Type
conf
DOI
10.1109/ICCCAS.2002.1179031
Filename
1179031
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