Title : 
How to group variables for reducing BDD
         
        
            Author : 
Zhang, Lei ; Lin, Zhenghui ; Lv, Zongwei
         
        
            Author_Institution : 
LSI Inst., Shanghai Jiao Tong Univ., China
         
        
        
        
            fDate : 
29 June-1 July 2002
         
        
        
            Abstract : 
The reduced order binary decision diagram (ROBDD) is widely used in logic synthesis and verification due to its special characteristics. Most algorithms using ROBDD have polynomial runtimes in the size of the ROBDD. ROBDD varies with different variable orders. So, finding a variable order to make ROBDD small is meaningful in digital circuit design. In this paper, we introduce a novel method to utilize variable relations efficiently. Moreover, for the first time, relations among variable sets are used to reduce BDD further, which is neglected in the past. Experiment results show that our algorithm is effective to reduce ROBDD.
         
        
            Keywords : 
binary decision diagrams; logic design; reduced order systems; BDD; ROBDD; digital circuit design; logic synthesis; logic verification; polynomial algorithm runtimes; reduced order binary decision diagram; symmetrical variable; variable orders; variable relations; variables grouping; Binary decision diagrams; Boolean functions; Circuit synthesis; Circuit testing; Data structures; Digital circuits; Large scale integration; Logic testing; Polynomials; Runtime;
         
        
        
        
            Conference_Titel : 
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
         
        
            Print_ISBN : 
0-7803-7547-5
         
        
        
            DOI : 
10.1109/ICCCAS.2002.1179037