Title :
Floorplanning consistent with partial-clustering on the sequence-pair
Author :
Zhu, Xiaoke ; Nakatake, Shigetoshi ; Kajitani, Yoji ; Ono, Nobuto
Author_Institution :
Univ. of Kitakyushu, Fukuoka, Japan
fDate :
29 June-1 July 2002
Abstract :
We propose a placement algorithm that cooperatively optimizes the wire-length and area, all on the sequence-pair. Wire-length minimization is pursued in the clustering stage, called partial clustering, in which modules are merged into the clusters according to the ratio-connectivity. Some modules are left as free-modules that are not so strongly connected to other modules. Area minimization is pursued by an iterative-improvement in which the move is partially hierarchical that exchanges the labels of free-modules, modules in the clusters, and clusters. In experiments, a behavior is clearly observed that free-modules creep into and out of clusters, adjusting the niches and humps in the clusters for area minimization with little effect on the wire-length.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; minimisation; modules; system-on-chip; area minimization; floorplanning; free module labels; merged modules; partial clustering; partially hierarchical iterative-improvement; placement algorithm; ratio-connectivity; sequence-pair partial-clustering; system on chip; wire-length minimization; wire-length optimization; Clustering algorithms; Creep; Data structures; Design optimization; Instruments; Partitioning algorithms; Very large scale integration;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179039