Title :
Hierarchical layout design of 8VSB chip
Author :
Han, Xiaoxia ; Zhu, Xinrong ; Zheng, Wei ; Zhang, Ming ; He, Qixin
Author_Institution :
Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China
fDate :
29 June-1 July 2002
Abstract :
8VSB chip is used to decode the ATSC compliant cable channel signals. This paper presents a new approach to hierarchical layout design of 8VSB chip. Experiments show that our method can accelerate timing convergence and shorten design period.
Keywords :
circuit layout CAD; decoding; integrated circuit layout; system-on-chip; 8VSB chip; ATSC compliant cable channel signal decoder; hierarchical layout design; system-on-chip; timing convergence; very deep submicron technology; Acceleration; Capacitance; Delay estimation; Helium; Information science; Iterative decoding; Libraries; Load modeling; Timing; Wire;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179045
