Title :
Hierarchical hard IP reuse in SOC
Author :
Yun, Chen ; Wei, Xiong ; Ping, Li
Author_Institution :
Inst. of Microelectron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fDate :
29 June-1 July 2002
Abstract :
A SOC design process with associated hierarchical hard IP reuse is proposed, in which hierarchical module partitioning can cope with the large scale of SOC. This methodology significantly reduces the time-to-market, complexity and potential for errors associated with SOC integration.
Keywords :
circuit CAD; industrial property; integrated circuit design; system-on-chip; SOC design; hierarchical hard IP reuse; module partitioning; Application specific integrated circuits; Consumer electronics; Hardware design languages; Intellectual property; Large-scale systems; Microelectronics; Process design; Silicon; Standards development; Time to market;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179052
