Design of a multi-channel high speed FIFO applied to HDLC processor based on PCI bus

In this paper, a design for a multi-channel high speed FIFO (First-in First-out) is presented. We know FIFO is widely used in various fields of data processing. Especially in the chip of high speed operation access, FIFO is a key device. This paper describes in detail data structure, algorithm and design method of the FIFO that is to support 128 logical channels and throughput maximum of 150 Mbps. The FIFO´s important feature is its structure of data buffer manager. The FIFO succeeds in functional simulation and timing verification on FPGA (Field Programmable Gate Array). Because the FIFO is applied to high speed HDLC based on PCI, its function is also tested successfully through FPGA under environment of a real-time operation system $VxWorks.