Title :
Design of DMA controller for multichannel PCI bus frame engine and data link manager
Author :
Qiao, Lufeng ; Wang, Zhigong
Author_Institution :
Southeast Univ., Nanjing, China
fDate :
29 June-1 July 2002
Abstract :
A new kind of PCI (Peripheral Component Interconnect) DMAC (direct memory access controller) is presented in this paper. It\´s an important part of "PCI bus HDLC frame engine and data link manager". Based on an instruction optimized embedded microprocessor, DMAC can meet the latency requirement perfectly with reasonable chip resources. The whole design is verified with Xilinx FPGA.
Keywords :
embedded systems; field programmable gate arrays; microcontrollers; peripheral interfaces; storage management chips; DMA controller; HDLC frame engine; Xilinx FPGA; data link manager; design verification; instruction optimized embedded microprocessor; latency; multichannel PCI bus; Bandwidth; Buffer storage; Control systems; Delay; Engines; Field programmable gate arrays; Frame relay; Memory management; Read-write memory; Wide area networks;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179059
