Title :
From packaging to fast timing simulators
Author_Institution :
ECE Dept., Dogus Univ., Istanbul, Turkey
Abstract :
When considering all the steps from packaging to verification of the design one is faced with many challenges ranging from the choice of the proper tools to model the device/interconnect physics, to high level simulations at the timing level. This paper starts by reviewing some of the tools available for extraction of device/interconnect parameters from their structure and shows how they are put to use in high level simulators such as ILLIADS-I.
Keywords :
SPICE; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; timing circuits; ILLIADS-I; design verification; device-interconnect parameters; device-interconnect physics; fast timing simulators; high level simulators; packaging; timing level; Analytical models; Circuit simulation; Delay effects; Integrated circuit interconnections; MOSFETs; Nonlinear equations; Packaging; RLC circuits; SPICE; Timing;
Conference_Titel :
Electromagnetic Compatibility, 2003. EMC '03. 2003 IEEE International Symposium on
Print_ISBN :
0-7803-7779-6
DOI :
10.1109/ICSMC2.2003.1429151
