A new VLSI implementation of the AES algorithm

In this paper, a new VLSI implementation of the AES (Rijndael) algorithm is described. With some proposed techniques, an optimized structure of the cipher is presented and optimizations of the algorithm´s encrypt/decrypt layers are discussed. The implementation is described in Verilog, synthesized by Synopsys tools and placed/routed by Cadence tools with 0.35 standard cell library. A simulation result shows that the core area of the chip is less than 8 mm2 which contains 113302 transistors and it can encrypt data at 66 Mhz with a 844 Mbps throughput, while decrypt data at 55 Mhz with a 704 Mbps throughput.