Title :
A new VLSI design for Viterbi decoder based on ASIP
Author :
Yi, Zhiqiang ; Xu, Yuamin ; Li, Yun ; Wang, Kuang
Author_Institution :
Dept. of Inf. & Electron. Eng., Zhejiang Univ., Hangzhou, China
fDate :
29 June-1 July 2002
Abstract :
Trellis Code Modulation (TCM) has been widely used because it can obtain 2.55∼7.37 dB coding gain without bandwidth expansion or reduction of the effective information rates. Since Viterbi decoder plays an important role in the realization of HDTV system, we conduct the research and development on integration of Viterbi decoder. This paper proposes a new VLSI design of Viterbi decoder using ASIPs based on hardware/software co-design idea. It reduces the total design time and enhances the reliability of VLSI. We have successfully used this method for the design of Viterbi decoder in the ASTC-HDTV receiver chip.
Keywords :
VLSI; Viterbi decoding; application specific integrated circuits; hardware-software codesign; high definition television; television receivers; trellis coded modulation; ASIP; ASTC-HDTV receiver chip; VLSI design; Viterbi decoder; hardware/software co-design; reliability; trellis code modulation; Application specific processors; Bandwidth; Convolutional codes; Decoding; Gain; HDTV; Information rates; Modulation coding; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179065
