DocumentCode :
317067
Title :
A parallel DSP testbed with a heterogeneous and reconfigurable network fabric
Author :
Tewksbury, S.K. ; Devabattini, K. ; Gandikota, V.
Author_Institution :
Dept. of Electr. & Comput. Eng., West Virginia Univ., Morgantown, WV, USA
fYear :
1997
fDate :
8-10 Oct 1997
Firstpage :
310
Lastpage :
322
Abstract :
A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SHARC DSPs), with a variety of parallel DSP array architectures possible. The network fabric is intended to be reconfigurable (within a rich but necessarily limited set of structures) to adapt to the needs of a sequence of image processing algorithms being executed (e.g., in a medical image processing environment). The testbed will exploit conventional FPGA components to provide reconfigurable network structures and will exploit commercial high-speed interconnect components emerging for applications such as board-to-board applications. As a computational accelerator, the testbed is intended to be controlled by a host processor, with the host processor cooperating in the definition of the changes in the structure of the network structure as execution of a sequence of image processing algorithms proceeds
Keywords :
digital signal processing chips; field programmable gate arrays; medical image processing; parallel architectures; reconfigurable architectures; Analog Devices SHARC DSP; FPGA; array architecture; computational accelerator; heterogeneous reconfigurable data network fabric; high-speed interconnect; image processing algorithm; large-grained processor; medical image processing; parallel DSP testbed; Biomedical image processing; Computer architecture; Computer networks; Concurrent computing; Digital signal processing; Fabrics; Field programmable gate arrays; Image processing; Life estimation; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1094-7116
Print_ISBN :
0-7803-4276-3
Type :
conf
DOI :
10.1109/ICISS.1997.630274
Filename :
630274
Link To Document :
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