A CMOS R-2R ladder digital-to-analog converter and its characterization

Author

Wang, Lei ; Fukatsu, Yasunori ; Watanabe, Kenzo

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

Volume

2

fYear

2001

fDate

2001

Firstpage

1026

Abstract

A digital-to-analog (D/A) converter based on the R-2R ladder is first analyzed in terms of the power consumption, to point out that the current-mode is the lowest power dissipation counter-part of the voltage-mode. The integral nonlinearity (INL) analysis and the characterization methods of the current-mode D/A converter are then presented to identify the error sources. The methods are applied to an 8-bit D/A converter fabricated using 0.6 μm CMOS process. Measured results compared with INL analysis indicate that the dominant error source of a prototype converter is the resistance of the metal interconnect between the ladder and the bonding pad, and INL of the ladder itself is 1.2 LSB

Keywords

CMOS integrated circuits; current-mode circuits; digital-analogue conversion; ladder networks; low-power electronics; power consumption; 8 bit; CMOS R-2R ladder D/A convertor; current-mode; error source; integral nonlinearity analysis; metal interconnect resistance; power consumption; resistance mismatch; transfer characteristics; voltage-mode; CMOS process; CMOS technology; Digital-analog conversion; Electrical resistance measurement; Energy consumption; Power dissipation; Resistors; Switches; Switching converters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2001. IMTC 2001. Proceedings of the 18th IEEE

Conference_Location

Budapest

ISSN

1091-5281

Print_ISBN

0-7803-6646-8

Type

conf

DOI

10.1109/IMTC.2001.928235

Filename

928235