Title :
A VLSI architecture for analog-to-residue conversion
Author :
Preethy, A.P. ; Radhakrishnan, D.
Author_Institution :
Nanyang Technol. Univ., Singapore
Abstract :
The design of a 16-bit A/R converter using two flash converter stages, incorporating an error correction mechanism, is given in this paper. The errors are corrected by modifying the existing PLA design as well as by including a digital error correction logic. The ROM requirement is equivalent to only a total of 90 bytes and the number of module adders is 16 and single bit binary adders is 4. The design uses only 40 voltage comparators for the two flash converter stages and is implemented using low power CMOS and pass logic
Keywords :
VLSI; PLA design; ROM requirement; VLSI architecture; analog-to-residue conversion; digital error correction logic; error correction mechanism; flash converter stages; low power CMOS; module adders; pass logic; single bit binary adders; voltage comparators;
Conference_Titel :
Advanced A/D and D/A Conversion Techniques and Their Applications, 1999. Third International Conference on (Conf. Publ. No. 466)
Conference_Location :
Glasgow
Print_ISBN :
0-85296-718-7
DOI :
10.1049/cp:19990469
