New structure of algorithmic DAC in switched current technique

Presents an architecture of algorithmic digital to analogue converter, which combines the advantages of the switched current technique and of the algorithmic design. It is fully compatible with digital VLSI CMOS technology, occupies little silicon area and dissipates low power. Moreover, it uses the new self-compensated memory cell which reduces CFT error and allows one to enlarge the bandwidth of memory cells and converters. A new DAC was developed and simulated results show a maximum sampling frequency of 12.5MHz with an accuracy of 10 bits