A complete framework for controller verification in manufacturing

Programmable Logic Controllers (PLCs) have been established as standard devices for automation and process control since the 1990s. Although a lot of research work has been done on the field of controller modeling and verification, it is still daily practice that control software is manually developed without applying formal validation methods. On the other hand, controller modeling is often seen detached from the plant or its model, i.e. as an open loop. The results of analysis of open-loop controller behavior give very little or almost no indications of the correct behavior of the closed-loop system. The contribution therefore proposes an approach to generate formal models out of PLC code. These controller models enable formal verification of the closed loop in combination with a specification. Due to the year of publication, all solution approaches are based on the syntax definition of the IEC 61131-3, which is not fulfilled by every industrial PLC vendor. Therefore, this contribution will show a way to use the defined xml formats of the Technical Committee 6 of the PLCopen as input for the formal model generation.