Regulus: A high performance VLSI architecture

Author

Sims, S. ; Benkual, J.

Author_Institution

Computer Consoles Inc., Irvine, CA, USA

fYear

1988

fDate

Feb. 29 1988-March 3 1988

Firstpage

48

Lastpage

50

Abstract

A description is given of the Regulus processor, a high-performance microprocessor designed to take full advantage of custom VLSI. The general-purpose 32-bit Regulus architecture is designed to minimize control area and maximize the amount of on-chip memory. The instruction set is very simple, with memory addressed only through load and store instructions. The first design is implemented with a 1.2- mu m double metal CMOS technology. The architecture is implemented with two full-custom CMOS VLSI devices, the instruction processor (IP) and the arithmetic processor (AP). Attention is focused on the IP chip, and some of the innovative features of its architecture and design are described.<>

Keywords

CMOS integrated circuits; instruction sets; microprocessor chips; 1.2 micron; 1.2- mu m double metal CMOS technology; 32 bit; Regulus processor; VLSI architecture; arithmetic processor; high-performance microprocessor; instruction processor; instruction set; load instructions; store instructions; Arithmetic; CMOS process; CMOS technology; Computer architecture; Decoding; High performance computing; Memory management; Microprocessors; Registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-0828-5

Type

conf

DOI

10.1109/CMPCON.1988.4826

Filename

4826