Title :
Subthreshold performance consideration of a novel architecture: ISEGaS deca-nanometer MOSFET
Author :
Kaur, Ravneet ; Chaujar, Rishu ; Saxena, Manoj ; Gupta, R.S.
Author_Institution :
Univ. of Delhi, New Delhi
Abstract :
The electrical behavior of deca-nanometer ISE MOSFET with gate stack: ISEGaS has been investigated and a computationally efficient analytical model using Evanescent Mode Analyses (EMA), for solving two-dimensional Poisson´s equation in the channel region, has been presented for accurate prediction of surface potential, electric field, subthreshold current and threshold voltage. An important short channel effect (SCE) - Drain Induced Barrier Lowering (DIBL) has been included in the model in a physically consistent manner, using Voltage Doping Transformation (VDT) method. The obtained analytical results have been verified by ATLAS 2D: device simulation software.
Keywords :
MOSFET; Poisson equation; gallium arsenide; nanoelectronics; semiconductor device models; ATLAS 2D; computationally efficient analytical model; deca-nanometer MOSFET; drain induced barrier lowering; electric field; evanescent mode analysis; short channel effect; subthreshold current; subthreshold performance; surface potential; threshold voltage; two-dimensional Poisson equation; voltage doping transformation method; Analytical models; Computer architecture; Dielectric substrates; Electric potential; MOSFET circuits; Performance analysis; Poisson equations; Semiconductor device doping; Semiconductor process modeling; Voltage; ATLAS 2D; EMA; ISEGaS; VDT;
Conference_Titel :
Physics of Semiconductor Devices, 2007. IWPSD 2007. International Workshop on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4244-1728-5
Electronic_ISBN :
978-1-4244-1728-5
DOI :
10.1109/IWPSD.2007.4472468
