• DocumentCode
    3171643
  • Title

    Design of asynchronous NoC using 3-port asynchronous T-routers

  • Author

    Kunapareddy, Sarvani ; Turaga, Sriraj Dheeraj ; Tej Mano Sajjan, Solomon Surya

  • Author_Institution
    Electr. & Comput. Eng., Univ. of Utah, Salt Lake City, UT, USA
  • fYear
    2015
  • fDate
    19-20 March 2015
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    The importance of a Network On Chip (NoC) is increasing rapidly with the advent of System on Chip (SoC) design using Intellectual Property (IP). This is because it is hard to communicate with the IPs as they have different timing constrains and data rates. Energy usage of the on-chip interconnects is also a concern for many such SoCs targeting portable battery powered devices which necessitates design of an efficient NoC. This paper proposes an energy efficient simple asynchronous NOC design using 3-port T routers. The router has three pairs of switch and merge modules, connected in a T fashion.
  • Keywords
    asynchronous circuits; logic design; network-on-chip; 3-port asynchronous T-routers; asynchronous NoC; data rates; energy usage; intellectual property; network on chip; on-chip interconnects; portable battery powered devices; system on chip design; timing constraints; Computers; Optical signal processing; Protocols; Switches; Synchronization; System-on-chip; Asynchronous; Handshake; Merge circuit; NOC; Network on chip; Router; Switch circuit;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuit, Power and Computing Technologies (ICCPCT), 2015 International Conference on
  • Conference_Location
    Nagercoil
  • Type

    conf

  • DOI
    10.1109/ICCPCT.2015.7159417
  • Filename
    7159417