An architecture and a simulator for parallel signal processing

The real-time implementation of many digital signal processing (DSP) algorithms requires novel algorithm mapping methods and architectures. Some of the architectures developed thus far include data-flow systems, systolic arrays, and wavefront arrays. Ideas from these architectures are combined with the concept of block data flow processing to present the block data flow architecture (BDFA). Key features of the BDFA include direct input/output to all processors, linear data-flow, and globally asynchronous operation. Use of the BDFA for 2-D filtering is presented and analyzed. The analysis is facilitated using timing results generated by a simulator developed with the C programming language. Development of the simulator is discussed in terms of how an architecture like the BDFA can be described and simulated in C. Simulation results show that the increase in throughput with the number of processors is nearly linear