Title :
Improved energy recovery logic for low power computation
Author :
Hongyu, Dai ; Runde, Zhou
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fDate :
29 June-1 July 2002
Abstract :
In this paper, we analyzed the power consumption in energy recovery circuits; the results show that the non-adiabatic loss is the main cause of power consumption. Based on this fact, an improved energy recovery logic (IERL) structure is proposed. IERL has an additional recovery path and reduces the non-adiabatic loss by improving the recovery percentage through the additional recovery path. From HSPICE simulation result, IERL circuits can greatly improve the low power performance. Complex gate design and cascading of IERL circuits are also considered and are easy to implement. A two-bit full adder of IERL and a sinusoidal power clock generator circuit were fabricated with 0.8 μm DPDM CMOS technology and are under test.
Keywords :
CMOS logic circuits; SPICE; adders; cascade networks; circuit complexity; circuit simulation; clocks; integrated circuit design; integrated circuit modelling; logic design; logic simulation; low-power electronics; 0.8 micron; DPDM CMOS technology; HSPICE simulation; IERL structure; cascaded IERL circuits; circuit testing; complex gate design; energy recovery circuit; energy recovery logic; full adder; low power computation; nonadiabatic loss; power consumption; power performance; recovery path; sinusoidal power clock generator circuit; CMOS logic circuits; CMOS technology; Capacitance; Circuit simulation; Circuit testing; Clocks; Energy consumption; Logic circuits; Power generation; Threshold voltage;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1179114
