A simulation methodology for the operational life time study of deep sub-micron technology integrated circuits using channel length dependent NBTI model

Negative Bias Temperature Instability (NBTI) is one of the key reliability issues for deep sub-micron semiconductor technologies. In this paper, geometry dependence on the NBTI performance of the PMOS FET is studied by conducting measurements on different FET geometries from a 65 nm CMOS technology. A channel length dependent NBTI model is derived based on this characterized data at different stress voltages. A simulation methodology is developed by implementing this model in the industry standard circuit simulator Mentor-Eldo with the User defined reliability model (UDRM) feature. This methodology is used to simulate the changes in the critical path delay of 65 nm high-speed SRAM memory products and to derive the guidelines for robust SRAM cell FET design against static noise margin (SNM) variations due to NBTI.