Title :
Nanoscale insulated shallow extension MOSFET with Dual Material Gate for high performance analog operations
Author :
Kaur, Ravneet ; Chaujar, Rishu ; Saxena, Manoj ; Gupta, R.S.
Author_Institution :
Univ. of Delhi, New Delhi
Abstract :
In this paper, for improving the analog performance of scaled MOS devices, structural design involving the integration of Dielectric Pocket (DP) and Dual Material Gate (DMG) onto the conventional MOSFET has been studied by means of Dual Material Gate Insulated Shallow Extension Gate Stack (DMG ISEGaS) MOSFET. Simulation results reveal that Dual Material Gate engineering down to 50 nm regime enhances the analog performance of the ISE architecture in terms of gm/IDS, early voltage (VEA) and intrinsic gain (gm/gd).
Keywords :
MOS analogue integrated circuits; MOSFET; nanoelectronics; ISE architecture; dielectric pocket; dual material gate engineering; high-performance analog operation; intrinsic gain; nanoscale insulated shallow extension MOSFET; scaled MOS devices; Dielectric devices; Dielectric materials; Dielectrics and electrical insulation; Intrusion detection; MOS devices; MOSFET circuits; Nanoscale devices; Performance gain; Permittivity; Voltage; ATLAS 2D; DMG; DP; ISEGaS;
Conference_Titel :
Physics of Semiconductor Devices, 2007. IWPSD 2007. International Workshop on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4244-1728-5
Electronic_ISBN :
978-1-4244-1728-5
DOI :
10.1109/IWPSD.2007.4472480
