DocumentCode
3171889
Title
A simplified distribution parasitic capacitance model for on-chip spiral inductors
Author
Masuda, Toru ; Kodama, Akihiro ; Nakamura, Takahiro ; Shiramizu, Nobuhiro ; Wada, Shin-ichiro ; Hashimoto, Takashi ; Washio, Katsuyoshi
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo
fYear
2006
fDate
18-20 Jan. 2006
Abstract
A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region
Keywords
Q-factor; equivalent circuits; inductors; semiconductor device models; Q-factor; distribution parasitic capacitance model; lumped equivalent circuit; on-chip spiral inductors; silicon monolithic spiral inductors; Equations; Equivalent circuits; Inductance; Inductors; Parasitic capacitance; Radio frequency; Shunt (electrical); Silicon; Spirals; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-9472-0
Type
conf
DOI
10.1109/SMIC.2005.1587920
Filename
1587920
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