Title :
WSI implementation of an 8-point FFT
Author :
Nienhaus, H.A. ; Landis, D.L.
Author_Institution :
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
A parallel architecture for a pipelineable 8-point fast Fourier transform (FFT) which used one-third fewer multiplications than a standard architecture is described. This architecture was developed for wafer-scale integration (WSI) implementation using 2-μm CMOS and laser restructurable VLSI. Equations for mapping an 8N-point FFT into a pipeline array of 8-point FFTs are presented
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; parallel architectures; pipeline processing; 8-point FFT; 8N-point FFT; CMOS; WSI implementation; laser restructurable VLSI; mapping; parallel architecture; pipeline array; pipelineable 8-point fast Fourier transform; Artificial intelligence; Delay effects; Equations; Flexible printed circuits; Pipelines;
Conference_Titel :
Southeastcon '90. Proceedings., IEEE
Conference_Location :
New Orleans, LA
DOI :
10.1109/SECON.1990.117915
