• DocumentCode
    3171958
  • Title

    Security through obscurity: An approach for protecting Register Transfer Level hardware IP

  • Author

    Chakraborty, Rajat Subhra ; Bhunia, Swarup

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA
  • fYear
    2009
  • fDate
    27-27 July 2009
  • Firstpage
    96
  • Lastpage
    99
  • Abstract
    Modern system-on-chip (SoC) designs rely heavily on reusable, verified and bug-free hardware intellectual property (IP) cores. Recent trends of IP piracy and reverse-engineering are causing major revenue loss to the IP vendors. A large majority of hardware IPs comes in register transfer level (RTL) description due to their portability and flexibility to map to any technology platform. In this paper, we propose a key-based security through obscurity approach for protecting RTL hardware IPs. The RTL design is first transformed into a technology-independent gate-level description and the functionality of the resulting gate-level netlist is then changed through modification of its state transition function. This process allows normal operation only on the successful application of a correct initialization sequence. The modified gate-level design is then decompiled to generate an obfuscated version of the RTL. Major RTL constructs and macros are optionally preserved through the transformation process using a forward annotation file. The proposed methodology differs from existing hardware obfuscation as well as watermarking techniques in its ability to achieve simultaneous functional and semantic obfuscation for RTL description of IP at low design overhead. Simulation results for a set of open-source IP cores show that we can achieve high levels of security through a well-formulated obfuscation scheme incurring nominal area, delay and power overhead.
  • Keywords
    industrial property; integrated circuit design; reverse engineering; security of data; system-on-chip; watermarking; IP piracy; bug-free hardware intellectual property cores; correct initialization sequence; key-based security; register transfer level description; register transfer level hardware IP; reverse engineering; system-on-chip designs; technology-independent gate-level description; watermarking techniques; Computer security; Cryptography; Design methodology; Hardware design languages; Open source software; Protection; Registers; Reverse engineering; System-on-a-chip; Watermarking; Hardware IP Protection; IP piracy; RTL obfuscation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware-Oriented Security and Trust, 2009. HOST '09. IEEE International Workshop on
  • Conference_Location
    Francisco, CA
  • Print_ISBN
    978-1-4244-4805-0
  • Electronic_ISBN
    978-1-4244-4804-3
  • Type

    conf

  • DOI
    10.1109/HST.2009.5224963
  • Filename
    5224963