An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits

Recently power dissipation (in addition to the earlier three aspects e.g. speed, size and cost) has become the main design concern in several applications. However, power saving should be achieved without compromising high performance or minimum area, thereby creating a new design culture for VLSI. Power consideration has been the ultimate design criteria in some special portable applications like pacemakers, mobile sets and wristwatches. As an attempt towards this, in the present work parallel back propagation artificial neural networks are employed to optimize and predict the various system parameter of a (In, Ga)As nanodevice so that the relevant device will exhibit better high frequency response and will be power efficient. Moreover prediction time is reduced using parallelism in ANN thereby making the design less time consuming.