DocumentCode
3172189
Title
A 2 GHz high IIP3 down-conversion mixer in 0.18-/spl mu/m CMOS
Author
Alam, Shaikh K. ; DeGroat, Joanne
Author_Institution
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH
fYear
2006
fDate
18-20 Jan. 2006
Abstract
This paper describes a CMOS mixer for a WCDMA front-end receiver in 0.18-mum CMOS. The mixer achieves a conversion gain of 16.6 dB and a double side band (DSB) NF of 13.8 dB. The mixer´s IIP3 is 12.12 dBm. The achieved low noise figure, gain and overall IIP3 fulfill the specifications for a UMTS mixer design. The mixer consumes 5 mA of current from a 1.8-V power supply
Keywords
3G mobile communication; CMOS analogue integrated circuits; MMIC mixers; code division multiple access; radio receivers; 0.18 micron; 1.8 V; 13.8 dB; 16.6 dB; 2 GHz; 5 mA; CMOS mixer; IIP3 down-conversion mixer; UMTS mixer design; WCDMA front-end receiver; analog integrated circuits; 3G mobile communication; CMOS technology; Circuits; Linearity; Mixers; Multiaccess communication; Noise measurement; Radio frequency; Transconductance; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-9472-0
Type
conf
DOI
10.1109/SMIC.2005.1587941
Filename
1587941
Link To Document