A Si bipolar 15 GHz static frequency divider and 10 Gb/s multiplexer

The authors describe a 16:1 divider consisting of four 2:1 divider stages and a 50- Omega output stage. The speed-limiting first stage is a master/slave D-flip-flop with inverter output fed back to the data input. The power consumption is 310 mW for the first stage, 190 mW for all three succeeding divider stages, and 40 mW for the output buffer. In contrast to III-V semiconductor dividers, the standard supply voltage of only 5 V is sufficient. The circuit design is based on an optimized 8:1 frequency divider yielding 8 GHz for a 2- mu m silicon bipolar technology with self-aligned emitter-base configuration. As is shown by the divider results, this technology is suited for data processing at high data rates, for which basic elements such as multiplexers, demultiplexers, D-flip-flops, etc. have been designed. The results indicate that data processing and communication based on ICs realized in advanced silicon bipolar technologies can be performed at data rates of 10 Gb/s and above.<>