• DocumentCode
    3172490
  • Title

    Parallel-array implementations of a non-restoring square root algorithm

  • Author

    Li, Yamin ; Chu, Wanming

  • Author_Institution
    Comput. Archit. Lab., Univ. of Aizu, Japan
  • fYear
    1997
  • fDate
    12-15 Oct 1997
  • Firstpage
    690
  • Lastpage
    695
  • Abstract
    In this paper we present a parallel-array implementation of a new non-restoring square root algorithm (PASQRT). The carry-save adder (CSA) is used in the parallel array. The PASQRT has several features unlike other implementations. First, it does not use redundant representation for square root result. Second, each iteration generates an exact resulting value. Next it does not require any conversion on the inputs of the CSA. And last, a precise remainder can be obtained immediately. Furthermore, we present an improved version-a root-select parallel-array implementation (RS-PASQRT) for fast result value generation. The RSPASQRT is capable of achieving up to about 150% speedup ratio over the PASQRT. The simplicity of the implementations indicates that the proposed approach is an alternative to consider when designing a fully pipelined square root unit
  • Keywords
    adders; digital arithmetic; parallel algorithms; carry-save adder; fully pipelined square root unit; nonrestoring square root algorithm; parallel array implementations; root-select parallel-array implementation; Circuits; Clocks; Concurrent computing; Equations; Hardware; Iterative algorithms; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-8206-X
  • Type

    conf

  • DOI
    10.1109/ICCD.1997.628940
  • Filename
    628940