Title :
A doubly-latched asynchronous pipeline
Author :
Kol, Rakefet ; Ginosar, Ran
Author_Institution :
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
Abstract :
DLAP, an asynchronous pipeline with master-slave (dual) registers, offers improved performance. It is most suitable for converting synchronous circuits into asynchronous ones. DLAP is capable of truly decoupled operation: All pipeline stages can shift data simultaneously, and execution is faster than previous designs when variable delays are encountered. Implementations based on both edge triggered registers and transparent latches are shown. STG and verified controllers are presented and simulated
Keywords :
asynchronous circuits; delays; flip-flops; logic CAD; doubly-latched asynchronous pipeline; edge triggered registers; master-slave registers; transparent latches; truly decoupled operation; variable delays; verified controllers; Asynchronous circuits; Clocks; Delay; Latches; Logic design; Master-slave; Pipelines; Registers; Signal design; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8206-X
DOI :
10.1109/ICCD.1997.628942
