A generalized test generation procedure for path delay faults

Recent studies suggest that it is necessary to generalize the test generation process for path delay faults in order to accommodate various effects that determine the worst-case delay of a path. However, these effects may be too complex to be captured accurately or considered explicitly, especially for large circuits. To alleviate this problem, we propose a test generation approach that generates multiple tests for each path delay fault based on a comprehensive set of conditions under which the worst-case delays are likely to occur. In this way, accurate modeling of delays is not necessary. We describe a specific test generation procedure to demonstrate this approach. The test generation procedure produces, for every target path, two-pattern tests where the first patterns bring every possible combination of values to the off-path inputs. We present experimental results to show the feasibility of a test generation procedure based on this approach.